(1) Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks and in which data is read or written by the local block.
(2) Description of the Related Art
Bit line hierarchy systems which enable a reduction of power consumption and high-speed processing in random access memories (RAMs) have been proposed. With these bit line hierarchy systems, a memory array is divided into a plurality of banks. A divided bit line in each bank is actually connected to a memory cell. A common bit line is located parallel to this divided bit line over each bank. A common bit line is not connected to a memory cell, so its load capacitance per unit length is smaller than that of a divided bit line. Therefore, compared with cases where bit lines are not hierarchized, these bit line hierarchy systems enable high-speed low-power read/write operation.
Conventional bit line hierarchy systems are disclosed in, for example, Low-power High-speed LSI Circuits & Technology, Sipec Corp. (the former Realize Inc.), 1998, p. 187, and Japanese Patent Laid-Open Publication No. 2000-207886.
FIG. 18 shows an example of a block diagram of a static RAM (SRAM) in which a bit line division system is adopted. As shown in FIG. 18, a conventional SRAM comprises a timing control circuit 1, a row decoder 2, a word line driver 3, a bank decoder 4, a column decoder 5, banks B1 through Bn, pre-charge circuits PC1 through PCp, column switches CS1 through CSp, and an I/O circuit 6.
The timing control circuit 1 inputs an address signal, clock signal, and control signal and controls the row decoder 2, bank decoder 4, column decoder 5, and pre-charge circuits PC1 through PCp on the basis of these signals.
The row decoder 2 decodes a row input address signal supplied from the timing control circuit 1, controls the word line driver 3 according, to the result, and selects predetermined memory cell groups in a row direction.
The column decoder 5 decodes a column input address signal supplied from the timing control circuit 1, controls the column switches CS1 through CSp according to the result, and selects predetermined memory cell groups.
The word line driver 3 selects predetermined memory cell groups in the row direction under the control of the row decoder 2.
Under the control of the timing control circuit 1 the bank decoder 4 controls bank control circuits BC1 through BCp included in each of the banks B1 through Bn for selecting them.
Each of the banks B1 through Bn includes a memory cell group divided by predetermined numbers (m's, in this example) in a column direction. When data is read or written, predetermined memory cells are selected by the word line driver 3. These memory cells are connected to the corresponding divided bit lines BL11 through BLp1, respectively, and are connected to the corresponding auxiliary divided bit lines BLX11 through BLXp1 respectively. Furthermore, predetermined banks are selected by the bank control circuits BC1 through BCp. These banks are connected to common bit lines GBL1 through GBLp, respectively, and are connected to auxiliary common bit lines GBLX1 through GBLXp respectively.
Memory cells (MCs) C11 through C1m, . . . , and Cp1 through Cpm are the smallest units that store data.
The bank control circuits BC1 through BCp go into the ON or OFF state under the control of the bank decoder 4 to connect the divided bit lines BL11 through BLp1 to the common bit lines GBL1 through GBLp, respectively, and to connect the auxiliary divided bit lines BLX11 through BLXp1 to the auxiliary common bit lines GBLX1 through GBLXp respectively.
The pre-charge circuits PC1 through PCp perform the pre-charge operation of supplying electric charges to the common bit lines GBL1 through GBLp and auxiliary common bit lines GBLX1 through GBLXp, which have lost electric charges, under the control of the timing control circuit 1 after read operation is completed.
The column switches CS1 through CSp go into the ON or OFF state under the control of the column decoder 5 to connect one of the common bit lines GBL1 through GBLp corresponding to a predetermined column to a data bus DB and to connect one of the auxiliary common bit lines GBLX1 through GBLXp corresponding to the predetermined column to an auxiliary data bus DBX.
The I/O circuit 6 includes a sense amplifier, write amplifier, and input-output circuit. The I/O circuit 6 amplifies read data with the sense amplifier and outputs it. Moreover, the I/O circuit 6 amplifies input data with the write amplifier and sends it to the data bus DB and auxiliary data bus DBX.
FIG. 18 shows the details of the bank B1 alone. The structure of the banks B2 through Bn is the same as that of the bank B1.
Now, operation in the above conventional SRAM will be described.
First, descriptions will be given with a case where data is read from the memory cell C11 as an example. When an address from which data is to be read is input to the timing control circuit 1, the timing control circuit 1 supplies a predetermined control signal to the row decoder 2, bank decoder 4, and column decoder 5 on the basis of this address.
The row decoder 2 decodes the row input address signal supplied from the timing control circuit 1 and informs the word line driver 3 about which word line the word line driver 3 should select.
The word line driver 3 puts a predetermined word line into an active state under the control of the row decoder 2. In this example, data is to be read from the memory cell C11, so a word line connected to the memory cells C11 through Cp1 is put into an active state and the other word lines are put into an inactive state.
Then data will be read from the memory cells C11 through Cp1 and output voltage will be applied to the divided bit lines BL11 through BLp1 and auxiliary divided bit lines BLX11 through BLXp1.
The bank decoder 4 puts all the bank control circuits BC1 through BCp included in the bank B1 into the ON state. As a result, the divided bit lines BL11 through BLp1 included in the bank B1 are connected to the common bit lines GBL1 through GBLp, respectively, and the auxiliary divided bit lines BLX11 through BLXp1 included in the bank B1 are connected to the auxiliary common bit lines GBLX1 through GBLXp respectively. Therefore, data stored in the memory cell C11 is supplied to the common bit line GBL1 and auxiliary common bit line GBLX1. In this case, the bank control circuits BC2 through BCp also go into the ON state, so data stored in the memory cells C21 through Cp1 is read and is output to the common bit lines GBL2 through GBLp, respectively, and to the auxiliary common bit lines GBLX2 through GBLXp respectively.
The column decoder 5 decodes the column input address signal supplied from the timing control circuit 1 and puts one of the column switches CS1 through CSp which corresponds to the result into the ON state. In this example, data stored in the memory cell C11 is to be read, so the column switch CS1 goes into the ON state and the others go into the OFF state.
Data output from the column switch CS1 is supplied to the I/O circuit 6 via the data bus DB and auxiliary data bus DBX.
The I/O circuit 6 increases the voltage of the data read in this way to a predetermined value with the built-in sense amplifier and outputs it.
The operation of reading data stored in another memory cell is performed in the same way as described above, so descriptions of it will be omitted. The operation of writing data into a memory cell is performed in the same way as described above, except that data is read from the I/O circuit 6 side and is supplied to a memory cell. Therefore, descriptions of it will also be omitted.
As stated above, compared with cases where bit lines are not hierarchized, the above bit line hierarchy system enables the provision of high-speed low-power semiconductor memories.
However, in recent years semiconductor memories which operate at higher speed are needed because the amount of information treated by information processing units has increased by leaps and bounds. Moreover, the miniaturization of portable information processing units is greatly needed, so the area of chips used in semiconductor memories must also be made smaller.